Today’s microprocessors need to compute more data than ever before, while maintaining a low power state for energy and battery life savings. Advanced Encryption Standard (AES) is one of the most compute-intensive block ciphers for media content protection and data encryption on high-performance tera-scale microprocessor platforms. The exponential increase in data rates of real-time media processing and computational complexities of mapping modular Galois-field (GF) arithmetic and arbitrary permutations onto general-purpose microprocessors create substantial power and performance bottlenecks within the CPU core. Recently, at Research@Intel Day, in Mountain View, California, Intel Researchers demonstrated an energy-efficient reconfigurable special-purpose hardware accelerator targeted for on-die real-time encryption/decryption of media content in 45nm high-K/Metal-gate CMOS technology. The prototype chip showcases novel high-performance reconfigurable arithmetic logic and data-path circuits that are capable of performing the most commonly employed AES-128, AES-192 and AES-256 encryption and decryption standards at industry-leading throughputs up to 53Gbps while consuming only 125mW. Near-threshold voltage optimized circuits utilized on this chip enable the encryption/decryption performance to scale over a wide operating voltage range from 1.1V down to 320mV. An all-digital variation-tolerant true random number generator design targeted for secure encryption key generation is also demonstrated functioning at 2.4Gbps. See more about research projects in Intel’s worldwide network of labs.